This invention relates to a method and apparatus for in-line testing a semiconductor wafer in the process of fabricating Very Larger Scale Integrated (VLSI) circuits and, more specifically, to a method and apparatus for automatically identifying during the front-end phase of a manufacturing line, the presence of defects, e.g., caused by silicon erosion.
The fabrication process of VLSI circuits includes a large number of manufacturing steps where defects may be created, leading to a circuit malfunction or low performance. Defects are attributable to a variety of causes, for instance, particles included in the photoresist, contamination introduced during a manufacturing step and silicon erosion. The latter is known to significantly affect the characteristics of semiconductor devices, particularly to FETs, creating an undesired high resistance in the source-drain region. Silicon erosion may be created during the following manufacturing steps. A gate stack, including a gate oxide and a polysilicon gate electrode, is formed on a silicon substrate followed by re-oxidation of the surface of the substrate to form a re-oxidized silicon layer. Sidewall spacers, including silicon nitride (Si3N4) or silicon dioxide (SiO2) are then formed on both sides of the gate stack for aligning ion implantation into the source and drain regions. The process of forming spacers includes the deposition of silicon nitride or silicon dioxide layers and etching the deposited layers. This etching is typically achieved by way of reactive ion etching (hereinafter referred to as “RIE”). Throughout the process of forming the spacers, the re-oxidized silicon layer is exposed to RIE, thereby reducing the thickness of the layer. Particularly, in the source and drain regions which are not covered by sidewall spacers, part of the re-oxidized silicon layer may be etched through into the silicon substrate. As a result, part of the silicon is removed, causing a defect in the silicon substrate.
FIG. 1A shows a cross-section of a conventional semiconductor wafer where no silicon erosion is observed. The structure includes gate stacks 110 on channel regions 132 formed on the silicon substrate 102. The gate stacks 110 consist of polysilicon electrodes 126 and silicon oxide layers 122 intervening between the silicon substrate 102 and the polysilicon electrodes 126. Re-oxidized layers 120 cover the side walls of the gate stacks 110 and extend to cover the edges of the source-drain regions 104. Spacers 112 are deposited adjacent to the side walls of the gate stacks 110. The respective spacers include sub-layers to form the spacers multilayer structure. The level of the upper surfaces 142 of the source-drain regions 104 coincide with the upper surface 144 of the silicon substrate.
FIG. 1B illustrates a cross-section of the semiconductor device in which silicon erosion 198 is seen in the source-drain region 154. Dotted line 192 shows the desired level of the upper surface of the silicon substrate 152 after formation of spacers 162. In the silicon erosion layer 198, the actual level of the surface of the silicon substrate 152 is lowered below the desired level 192 due to the unwanted removal of silicon. The depth of the defect in the silicon erosion may be as larger as 5 nm. Such silicon erosion leads to a high resistance of the source-drain region 154. The increase in resistance is caused by a high concentration of doping located near the surface.
In accordance with conventional manufacturing practices, the wafer test and evaluation of the wafer is performed after completing the wafer, as will be described hereinafter.
Manufacturing a semiconductor VLSI begins with setting a silicon wafer on a production line. Subsequent processes can be broadly classified into wafer processing, assembling and testing. The wafer process typically includes a front-end of the line (FEOL) process, a back-end of the line (BEOL) process, followed by a good chip/wafer (G/W) test of the wafer. During FEOL, an epitaxial layer, an isolation layer, a well, a gate insulating layer, a gate electrode, spacers adjacent the gate electrode and source drain regions are sequentially formed on the wafer. Then, the surfaces of the source-drain regions are silicided. Next, the manufacturing process moves to BEOL where metal wiring is provided above the semiconductor structure on the wafer, followed by a passivation layer formed on the topmost layer, completing the wafer.
The wafer is evaluated based on inspection techniques, such as the G/W test, followed by assembly and test. The G/W test identifies the good (or bad) semiconductor chips formed on the wafer. It is performed subsequent to completing the wafer, and follows the formation of all the elements, such as semiconductor structures, interlayer dielectric, electrode contact metallization, that are necessary for the subsequent back-end of the line.
The G/W test generally consists of the following steps. First, the wafer is positioned on a stage for inspection. A probe card is then applied to the wafer, and inspection probes are brought in contact with respective contact pads on the IC chips formed in the wafer. Next, input signals are applied to the IC chips through the inspection probes to observe the electrical signals as seen at the primary outputs of the ICs. Depending on the responses, it is determined whether or not respective ICs on the wafer have the desired characteristics and performance. However, as previously mentioned, silicon erosion may already have been created in an earlier process, e.g., during the formation of the spacers adjacent the gate stack, before forming the upper structures, such as interlayer dielectric and electrode contact metallization. Although, as mentioned previously, silicon erosion causes a significant deterioration in performance and characteristics of the ICs, wafers including bad chips cannot be identified until the wafer process terminates, i.e., in the G/W test following the BEOL phase. This results in a waste of resources by completing bad wafers to their very end.
In addition to the final G/W test of the wafer, other in-line tests are typically performed during the wafer process in real-time by using structures formed in unoccupied spaces between the IC chips on the wafer. By way of example, and referring to FIG. 2, there is shown wafer 200 and a partially enlarged view thereof. In the upper section of the figure, grid lines 252 represent unoccupied spaces. During the dicing process subsequent to BEOL, the wafer is cut alongside unoccupied spaces between the individual IC chips. Some of the unoccupied spaces 252 include test regions 211, 212, 213, referred to “kerfs”. In the lower portion of the figure, kerfs are represented by shaded rectangles between IC chips 201, 202, 203. The kerfs are subject to the same process manufacturing steps as the semiconductor structures in the IC chips. Therefore, an examination of the electrical characteristics during the wafer process and the occurrence of defects created in IC chips adjacent the respective kerfs can be determined. These are characteristic of defaults found anywhere in the wafer.
FIG. 3A shows a block diagram of a typical system to perform an in-line test. The system includes a tester 302, a space transformer 304 and an inspection probe 312. The tester 302 is computer driven and is set to execute an in-line test program. The tester 302 is connected to space transformer 304 via communication line 303. The space transformer 304 is further attached to inspection probe 312 via a driving mechanism 310 which couples the communication line 303 between the space transformer 304 and the inspection probe 312. The tester 302 controls the space transformer 304 in accordance with the program. In response to a request from the program, the space transformer 302 moves the inspection probe 312.
FIG. 3B shows an enlarged view of a section of the inspection probe 312 and kerf 390 illustrated in FIG. 3A. The inspection probe 312 is equipped with electrodes 362, 364, 366, 368, 370 spanning from the bottom surface of the inspection probe 312 opposite to the upper surface of the wafer 300. Electrodes are connected to the tester 302 through lines 303, 310 and space transformer 304 so that the tester can apply desired voltages to the electrodes in accordance with the program, allowing the tester to detect signals from the electrodes. The kerf 390 further includes a semiconductor structure 301 for testing and portions of the semiconductor structure connected to conductive pads 322, 324, 326, 328, 330.
In accordance with the in-line test program, inspection probe 312 is positioned to make contact with electrodes 362, 364, 366, 368, 370 and corresponding conductive pads 322, 324, 326, 328, 330. The tester 302 applies a predetermined input through the electrodes to the semiconductor structure 301 and observes the response signals from the semiconductor structure 301 through the conductive pads and electrodes. By analyzing the response signals, the program determines the condition of the wafer 300 in the production line.
According to conventional in-line testing, the presence of undetected defective devices leads to a considerable expenditure of resources to complete the formation of defective devices, followed by testing and identification in a wafer map.
Accordingly, there is a distinct need in industry for a method of identifying and a system for enabling such a methodology to eliminate defective devices early in the manufacturing process in order to increase the throughput and avoid wasting resources on devices that will eventually be scrapped. Therefore, it is desired to identify bad wafers in earlier stage of the wafer process.
Following are listed several patents that address various aspects of the aforementioned problems.
U.S. Pat. No. 6,673,640 to Naruoka describes a method of evaluating a crystal defect in a thin film SOI layer using an in-line test. Crystal defects are elucidated by transferring metal into the defects, followed by irradiation by laser beam of the SOI layer to cause excess carriers. The excess carriers are separated by applying a voltage to an interface between each defects and silicon of the SOI layer so that the excess carries are turned into an electric current. By measuring the electric current, defects in the SOI layer are evaluated. However, the patent does not mention the distribution of the measured currents in the SOI layer nor evaluates the defects based on the measured current distribution.
U.S. Pat. No. 6,350,636 to Lee et al. discloses a method for forming suicide test structures to monitor and evaluate the quality of semiconductive junctions after the formation of a silicide layer over the junction. The patent discloses specially designed test structures formed for in-line testing in the kerf of an IC wafer. A test structures is designed to measure the bulk junction leakage by having a silicide contact layer spaced away from the junction edge. The remainder of the test structure measures the edge related junction leakage, and is provided with a serpentine edge which the silicide layer extends to, and plural interior openings. However, the patent does not describe a test structure having a source-drain region between polysilicon gate stacks, which allows measurement of leakage current between the polysilicon gate stack and the source-drain region.
U.S. Pat. No. 6,315,574 to Kamieniecki et al. discloses an apparatus to perform real-time, in-line testing of semiconductor wafers during a manufacturing process. A source of light impinges upon the wafer as the wafer passes to an adjacent probe assembly, and the apparatus measures various electrical characteristics of the wafer based on the surface photo-voltage induced by light. There is no description of leakage current voltage between the gate stack and the source-drain region or use of the measured leakage current to determine the quality of the wafer.